TANNO Koichi

写真a

Affiliation

Vice President Vice President

Title

Professor

External Link

Degree 【 display / non-display

  • Doctor (Engineering) ( 1999.9   Kumamoto University )

  • 修士(工学) ( 1992.3   宮崎大学 )

Research Areas 【 display / non-display

  • Manufacturing Technology (Mechanical Engineering, Electrical and Electronic Engineering, Chemical Engineering) / Electron device and electronic equipment

 

Papers 【 display / non-display

  • The Fractional-N All Digital Frequency Locked Loop with Robustness for PVT Variation and Its Application for the Microcontroller Unit Reviewed

    MIYAUCHI Ryoichi, YOSHIDA Akio, NAKANO Shuya, TAMURA Hiroki, TANNO Koichi, FUKUCHI Yutaka, KAWAMURA Yukio, KODAMA Yuki, SEKIYA Yuichi

    IEICE Transactions on Information and Systems   E104D ( 8 )   1146 - 1153   2021

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    Authorship:Corresponding author   Language:English   Publishing type:Research paper (scientific journal)   Publisher:The Institute of Electronics, Information and Communication Engineers  

    This paper describes the Fractional-N All Digital Frequency Locked Loop (ADFLL) with Robustness for PVT variation and its application for the microcontroller unit. The conventional FLL is difficult to achieve the required specification by using the fine CMOS process. Especially, the conventional FLL has some problems such as unexpected operation and long lock time that are caused by PVT variation. To overcome these problems, we propose a new ADFLL which uses dynamic selecting digital filter coefficients. The proposed ADFLL was evaluatied through the HSPICE simulation and fabricating chips using a 0.13 µm CMOS process. From these results, we observed the proposed ADFLL has robustness for PVT variation by using dynamic selecting digital filter coefficient, and the lock time is improved up to 57%, clock jitter is 0.85 nsec.

    DOI: 10.1587/transinf.2020LOP0008

    Scopus

    CiNii Research

  • Novel Fractional-N All Digital Frequency Locked Loop with Robustness for PVT variation Reviewed

    Ryoichi Miyauchi, Akio Yoshida, Shuya Nakano, Hiroki Tamura, Koichi Tanno, Yutaka Fukuchi, Yukio Kawamura, Yuki Kodama, and Yuichi Sekiya

    IEEE 50th International Symposium on Multiple-Valued Logic (ISMVL 2020)   2020-November   159 - 163   2020.11

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    Authorship:Corresponding author   Language:English   Publishing type:Research paper (international conference proceedings)   Publisher:Proceedings of The International Symposium on Multiple-Valued Logic  

    This paper describes a novel Fractional-N all digital frequency locked loop (ADFLL) with robustness for PVT variation. The conventional FLL is difficult to achieve the required specification by using the fine CMOS process. Especially, the conventional FLL has some problems such as unexpected operation and long lock time that are caused by PVT variation. To overcome these problems, we propose a new ADFLL which uses dynamic selecting digital filter coefficient. The proposed ADFLL evaluated through the HSPICE simulation using 0.13 μm CMOS process. From simulation results, the proposed ADFLL has robustness for PVT variation, and the lock time is improved up to 57%.

    DOI: 10.1109/ISMVL49045.2020.00-12

    Scopus

  • A Test Fabrication and Measurement Results of Low Voltage CMOS Current Mode Reference Circuit Based on Subthreshold Operation Reviewed

    Kenya Kondo, Koichi Tanno

    The 35th International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC2020)   25 - 29   2020.7

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    Authorship:Corresponding author   Language:English   Publishing type:Research paper (international conference proceedings)   Publisher:ITC-CSCC 2020 - 35th International Technical Conference on Circuits/Systems, Computers and Communications  

    This paper presents the measurement results of the low voltage CMOS current mode reference circuit which is designed using subthreshold operation of MOSFETs. This circuit ensures adjustment the temperature coefficient and the output voltage after fabrication by the trimming function. The proposed reference circuit has been designed and fabricated using 1-poly 2-metal 0.6 μm standard CMOS process. The silicon characteristics have been measured for the supply voltage range of 0 V to 3.6 V and the temperature range of -20 °C to 100 °C. The silicon measurement results of eight samples show the average output voltage of 0.54 V and the variation of 2.1 % before trimming compared with the typical design simulation of 0.50 V. And the supply voltage range is from 1.1 V to 3.6 V in spite of using 0.6 μm standard CMOS process. Although the output voltage and the temperature coefficient of the silicon results show the discrepancy from the simulation result, we could demonstrate that the output voltage can be adjusted to the target characteristic by trimming function.

    Scopus

  • Automatic Sleep Disorders Classification Using Ensemble of Bagged Tree Based on Sleep Quality Features Reviewed

    Edita Rosana Widasari, Koichi Tanno, Hiroki Tamura

    Electronics   9 ( 3 )   512-1 - 512-20   2020.3

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    Authorship:Corresponding author   Language:English   Publishing type:Research paper (scientific journal)   Publisher:Electronics (Switzerland)  

    Sleep disorder is a medical disease of the sleep patterns, which commonly suffered by the elderly. Sleep disorders diagnosis and treatment are considered to be challenging due to a time-consuming and inconvenient process for the patient. Moreover, the use of Polysomnography (PSG) in sleep disorder diagnosis is a high-cost process. Therefore, we propose an efficient classification method of sleep disorder by merely using electrocardiography (ECG) signals to simplify the sleep disorders diagnosis process. Different from many current related studies that applied a five-minute epoch to observe the main frequency band of the ECG signal, we perform a pre-processing technique that suitable for the 30-seconds epoch of the ECG signal. By this simplification, the proposed method has a low computational cost so that suitable to be implemented in an embedded hardware device. Structurally, the proposed method consists of five stages: (1) pre-processing, (2) spectral features extraction, (3) sleep stage detection using the Decision-Tree-Based Support Vector Machine (DTB-SVM), (4) assess the sleep quality features, and (5) sleep disorders classification using ensemble of bagged tree classifiers. We evaluate the effectiveness of the proposed method in the task of classifying the sleep disorders into four classes (insomnia, Sleep-Disordered Breathing (SDB), REM Behavior Disorder (RBD), and healthy subjects) from the 51 patients of the Cyclic Alternating Pattern (CAP) sleep data. Based on experimental results, the proposed method presents 84.01% of sensitivity, 94.17% of specificity, 86.27% of overall accuracy, and 0.70 of Cohen’s kappa. This result indicates that the proposed method able to reliably classify the sleep disorders merely using the 30-seconds epoch ECG in order to address the issue of a multichannel signal such as the PSG.

    DOI: 10.3390/electronics9030512

    Scopus

  • High-PSRR, Low-Voltage CMOS Current Mode Reference Circuit Using Self-Regulator with Adaptive Biasing Technique Reviewed

    KONDO Kenya, TAMURA Hiroki, TANNO Koichi

    IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences   E103A ( 2 )   486 - 491   2020

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    Authorship:Corresponding author   Language:English   Publishing type:Research paper (scientific journal)   Publisher:The Institute of Electronics, Information and Communication Engineers  

    In this paper, we propose the low voltage CMOS current mode reference circuit using self-regulator with adaptive biasing technique. It drastically reduces the line sensitivity (LS) of the output voltage and the power supply voltage dependence of the temperature coefficient (TC). The self-regulator used in the proposed circuit adaptively generates the minimum voltage required the reference core circuit following the PVT (process, voltage and temperature) conditions. It makes possible to improve circuit performances instead of slightly increasing minimum power supply voltage. This proposed circuit has been designed and evaluated by SPICE simulation using TSMC 65nm CMOS process with 3.3V (2.5V over-drive) transistor option. From simulation results, LS is reduced to 0.0065%/V under 0.8V < <i>V<sub>DD</sub></i> < 3.0V. TC is 67.6ppm/°C under the condition that the temperature range is from -40°C to 125°C and <i>V<sub>DD</sub></i> range is from 0.8V to 3.0V. The power supply rejection ratio (PSRR) is less than -80.4dB when <i>V<sub>DD</sub></i> is higher than 0.8V and the noise frequency is 100Hz. According to the simulation results, we could confirm that the performances of the proposed circuit are improved compared with the conventional circuit.

    DOI: 10.1587/transfun.2019EAP1061

    Scopus

    CiNii Research

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Books 【 display / non-display

  • 福岡システムLSIカレッジ「アナログ回路基礎」

    石塚興彦, 淡野公一, 武藤浩二,太郎丸 眞( Role: Joint author)

    財団法人 福岡県産業・科学技術振興財団  2011.5 

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    Language:Japanese Book type:Textbook, survey, introduction

  • システムLSI設計技術者養成講座基本課程 「バイポーラトランジスタ回路の基礎」

    淡野公一, 武藤浩二, 石塚興彦( Role: Joint author)

    財団法人 福岡県産業・科学技術振興財団  2011.5 

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    Language:Japanese Book type:Textbook, survey, introduction

  • システムLSI設計技術者養成講座基本課程 アナログ設計コースII「汎用アナログ電子回路」

    石塚興彦, 淡野公一, 武藤浩二( Role: Joint author)

    財団法人 福岡県産業・科学技術振興財団  2009.4 

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    Language:Japanese Book type:Textbook, survey, introduction

  • 基礎課程 アナログ設計Iコース

    石塚 興彦, 淡野 公一( Role: Joint author)

    福岡システムLSIカレッジ編  2001.11 

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    Language:Japanese Book type:Textbook, survey, introduction

MISC 【 display / non-display

  • [解説] ヘルスケア機器とそれを支えるデバイス技術 Invited Reviewed

    淡野 公一, 田村 宏樹

    「システム/制御/情報」   61 ( 8 )   334 - 339   2017.8

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    Language:Japanese   Publishing type:Article, review, commentary, editorial, etc. (scientific journal)  

Presentations 【 display / non-display

  • トマト着果のためのホルモン剤の自動噴霧実験および噴霧器の温湿度依存に関する考察

    河村 昂大, 川野 智希, 西 啓太, 川崎 悠人, 小林 太一, 福重 博貴, 藤岡 想, 淡野 公一

    電子情報通信学会 総合大会  2024.3.6 

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    Event date: 2024.3.4 - 2024.3.8

    Language:Japanese   Presentation type:Oral presentation (general)  

  • トマト着果のためのホルモン剤の自動噴霧実験及び希釈倍率に関する研究

    川野 智希, 河村 昂太, 川﨑 悠人, 小林 太一, 福重 博貴, 藤岡 想, 淡野 公一

    日本生物環境工学会九州支部2023年北九州大会(第16回)  2023.12.16 

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    Event date: 2023.12.16

    Language:Japanese   Presentation type:Poster presentation  

  • 多入力FG-MOSFETの初期電荷除去法とその考察

    熊谷 雅哉, 外山 貴子, 淡野 公一

    2023年度(第76回)電気・情報関係学会九州支部連合大会  2023.9.8 

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    Event date: 2023.9.7 - 2023.9.8

    Language:Japanese   Presentation type:Oral presentation (general)  

  • ホルモン剤噴霧の自動化に向けた4-クロロフェノキシ酢酸の希釈倍率に関する検討

    川野 智希, 河村 昂大, 川﨑 悠人, 小林 太一, 福重 博貴, 藤岡 想, 淡野 公一

    2023年度(第76回)電気・情報関係学会九州支部連合大会  2023.9.8 

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    Event date: 2023.9.7 - 2023.9.8

    Language:Japanese   Presentation type:Oral presentation (general)  

  • 2段構成CMOSオペアンプのための新たなシステマティックオフセット電圧低減手法

    有村 知将, 淡野 公一

    2023年度(第76回)電気・情報関係学会九州支部連合大会  2023.9.8 

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    Event date: 2023.9.7 - 2023.9.8

    Language:Japanese   Presentation type:Oral presentation (general)  

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Awards 【 display / non-display

  • ベストポスター賞

    2023.12   令和5年度日本生物環境工学会九州支部大会   トマト着果のためのホルモン剤の自動噴霧実験及び希釈倍率に関する研究

    川野 智希, 河村 昂大, 川崎 悠人, 小林 太一, 福重 博貴, 藤岡 想, 淡野 公一

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    Award type:Award from Japanese society, conference, symposium, etc.  Country:Japan

  • 宮崎大学教員教育活動表彰

    2021.1   宮崎大学   宮崎大学教員教育活動表彰

    淡野 公一

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    Country:Japan

  • Best Paper Award

    2020.10   Organizing Committee of ITC-CSCC  

    Kenya Kondo, Koichi Tanno

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    Award type:Award from international society, conference, symposium, etc.  Country:Japan

  • 2019年度「日本政府観光局(JNTO) 国際会議誘致・開催貢献賞」

    2020.2   日本政府観光局  

    SMC2018実行委員会(代表:淡野 公一)

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    Country:Japan

  • Best Student Paper Award - FInalist

    2019.10   IEEE Systems, Man, and Cybernetics Society  

    Edita Rosana Widasari, Koichi Tanno, Hiroki Tamura

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    Award type:Award from international society, conference, symposium, etc.  Country:United States

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Grant-in-Aid for Scientific Research 【 display / non-display

  • 光とナノミストを利用した連続水素生産装置の開発

    Grant number:20K05695  2020.04 - 2023.03

    独立行政法人日本学術振興会  科学研究費補助金  基盤研究(C)

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    Authorship:Coinvestigator(s) 

  • 企業が理工系人材に求めるコンピテンシーと大学に求めるカリキュラム

    Grant number:19K02891  2019.04 - 2022.03

    科学研究費補助金  基盤研究(C)

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    Authorship:Coinvestigator(s) 

  • ナノミスト噴霧器を用いた統合型農業補助システムの構築

    Grant number:18K05908  2018.04 - 2023.03

    独立行政法人日本学術振興会  科学研究費補助金  基盤研究(C)

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    Authorship:Principal investigator 

  • 圧電素子を用いた学習機能を有するベッド上での心拍・呼吸・体動検出システムの開発

    Grant number:18K11531  2018.04 - 2021.03

    科学研究費補助金  基盤研究(C)

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    Authorship:Coinvestigator(s) 

  • アナログLSI設計者育成のための新しい教育システム開発と授業・公開講座の実施

    Grant number:17K01008  2017.04 - 2021.03

    科学研究費補助金  基盤研究(C)

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    Authorship:Coinvestigator(s) 

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Available Technology 【 display / non-display