論文 - 淡野 公一
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Miyauchi R., Yoshida A., Nakano S., Tamura H., Tanno K., Fukuchi Y., Kawamura Y., Kodama Y., Sekiya Y.
IEICE Transactions on Information and Systems E104D ( 8 ) 1146 - 1153 2021年
担当区分：責任著者 記述言語：英語 掲載種別：研究論文（学術雑誌） 出版者・発行元：IEICE Transactions on Information and Systems
This paper describes the Fractional-N All Digital Frequency Locked Loop (ADFLL) with Robustness for PVT variation and its application for the microcontroller unit. The conventional FLL is difficult to achieve the required specification by using the fine CMOS process. Especially, the conventional FLL has some problems such as unexpected operation and long lock time that are caused by PVT variation. To overcome these problems, we propose a new ADFLL which uses dynamic selecting digital filter coefficients. The proposed ADFLL was evaluatied through the HSPICE simulation and fabricating chips using a 0.13 µm CMOS process. From these results, we observed the proposed ADFLL has robustness for PVT variation by using dynamic selecting digital filter coefficient, and the lock time is improved up to 57%, clock jitter is 0.85 nsec.
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Novel Fractional-N All Digital Frequency Locked Loop with Robustness for PVT variation 査読あり
Ryoichi Miyauchi, Akio Yoshida, Shuya Nakano, Hiroki Tamura, Koichi Tanno, Yutaka Fukuchi, Yukio Kawamura, Yuki Kodama, and Yuichi Sekiya
IEEE 50th International Symposium on Multiple-Valued Logic (ISMVL 2020) 2020-November 159 - 163 2020年11月
担当区分：責任著者 記述言語：英語 掲載種別：研究論文（国際会議プロシーディングス） 出版者・発行元：Proceedings of The International Symposium on Multiple-Valued Logic
This paper describes a novel Fractional-N all digital frequency locked loop (ADFLL) with robustness for PVT variation. The conventional FLL is difficult to achieve the required specification by using the fine CMOS process. Especially, the conventional FLL has some problems such as unexpected operation and long lock time that are caused by PVT variation. To overcome these problems, we propose a new ADFLL which uses dynamic selecting digital filter coefficient. The proposed ADFLL evaluated through the HSPICE simulation using 0.13 μm CMOS process. From simulation results, the proposed ADFLL has robustness for PVT variation, and the lock time is improved up to 57%.
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Kenya Kondo, Koichi Tanno
The 35th International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC2020) 25 - 29 2020年7月
担当区分：責任著者 記述言語：英語 掲載種別：研究論文（国際会議プロシーディングス） 出版者・発行元：ITC-CSCC 2020 - 35th International Technical Conference on Circuits/Systems, Computers and Communications
This paper presents the measurement results of the low voltage CMOS current mode reference circuit which is designed using subthreshold operation of MOSFETs. This circuit ensures adjustment the temperature coefficient and the output voltage after fabrication by the trimming function. The proposed reference circuit has been designed and fabricated using 1-poly 2-metal 0.6 μm standard CMOS process. The silicon characteristics have been measured for the supply voltage range of 0 V to 3.6 V and the temperature range of -20 °C to 100 °C. The silicon measurement results of eight samples show the average output voltage of 0.54 V and the variation of 2.1 % before trimming compared with the typical design simulation of 0.50 V. And the supply voltage range is from 1.1 V to 3.6 V in spite of using 0.6 μm standard CMOS process. Although the output voltage and the temperature coefficient of the silicon results show the discrepancy from the simulation result, we could demonstrate that the output voltage can be adjusted to the target characteristic by trimming function.
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Edita Rosana Widasari, Koichi Tanno, Hiroki Tamura
Electronics 9 ( 3 ) 512-1 - 512-20 2020年3月
担当区分：責任著者 記述言語：英語 掲載種別：研究論文（学術雑誌） 出版者・発行元：Electronics (Switzerland)
Sleep disorder is a medical disease of the sleep patterns, which commonly suffered by the elderly. Sleep disorders diagnosis and treatment are considered to be challenging due to a time-consuming and inconvenient process for the patient. Moreover, the use of Polysomnography (PSG) in sleep disorder diagnosis is a high-cost process. Therefore, we propose an efficient classification method of sleep disorder by merely using electrocardiography (ECG) signals to simplify the sleep disorders diagnosis process. Different from many current related studies that applied a five-minute epoch to observe the main frequency band of the ECG signal, we perform a pre-processing technique that suitable for the 30-seconds epoch of the ECG signal. By this simplification, the proposed method has a low computational cost so that suitable to be implemented in an embedded hardware device. Structurally, the proposed method consists of five stages: (1) pre-processing, (2) spectral features extraction, (3) sleep stage detection using the Decision-Tree-Based Support Vector Machine (DTB-SVM), (4) assess the sleep quality features, and (5) sleep disorders classification using ensemble of bagged tree classifiers. We evaluate the effectiveness of the proposed method in the task of classifying the sleep disorders into four classes (insomnia, Sleep-Disordered Breathing (SDB), REM Behavior Disorder (RBD), and healthy subjects) from the 51 patients of the Cyclic Alternating Pattern (CAP) sleep data. Based on experimental results, the proposed method presents 84.01% of sensitivity, 94.17% of specificity, 86.27% of overall accuracy, and 0.70 of Cohen’s kappa. This result indicates that the proposed method able to reliably classify the sleep disorders merely using the 30-seconds epoch ECG in order to address the issue of a multichannel signal such as the PSG.
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Kondo K., Tamura H., Tanno K.
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences E103A ( 2 ) 486 - 491 2020年
担当区分：責任著者 記述言語：英語 掲載種別：研究論文（学術雑誌） 出版者・発行元：IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
In this paper, we propose the low voltage CMOS current mode reference circuit using self-regulator with adaptive biasing technique. It drastically reduces the line sensitivity (LS) of the output voltage and the power supply voltage dependence of the temperature coefficient (TC). The self-regulator used in the proposed circuit adaptively generates the minimum voltage required the reference core circuit following the PVT (process, voltage and temperature) conditions. It makes possible to improve circuit performances instead of slightly increasing minimum power supply voltage. This proposed circuit has been designed and evaluated by SPICE simulation using TSMC 65 nm CMOS process with 3.3V (2.5V over-drive) transistor option. From simulation results, LS is reduced to 0.0065%/V under 0.8V < VDD < 3.0V. TC is 67.6 ppm/°C under the condition that the temperature range is from -40°C to 125°C and VDD range is from 0.8V to 3.0V. The power supply rejection ratio (PSRR) is less than -80:4 dB when VDD is higher than 0.8V and the noise frequency is 100 Hz. According to the simulation results, we could confirm that the performances of the proposed circuit are improved compared with the conventional circuit.
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宮崎大学における共同研究の相手先の地理的分布 査読あり
西片 奈保子, 竹下 哲史, 川崎 一正, 秋丸 國廣, 甲藤 正人, 淡野 公一, 北村 寿宏
産学連携学 21 ( 1 ) 1_29 - 1_44 2024年12月
記述言語：日本語 掲載種別：研究論文（学術雑誌） 出版者・発行元：特定非営利活動法人 産学連携学会
宮崎大学の共同研究の状況について，2009～2018（平成21～30）年度の契約データに基づき，相手先やその地域性，研究費受入額などの分析を行った結果，以下のことが明らかになった．①宮崎大学の共同研究の件数における相手先の割合は，大企業が約49％，中小企業が約36％，企業以外が約15％であり，大企業の割合が最も高くなっている．②大企業を相手先とする共同研究の件数は，関東，近畿，東海，九州・沖縄，中国の各地方，宮崎県の順に多い．関東地方や宮崎県では概ね横ばい傾向であるが，東海，近畿，九州・沖縄の各地方では2014～15年度頃から増加に転じているとみられる．③中小企業を相手先とする共同研究の件数は，宮崎県，関東地方，近畿地方，九州・沖縄地方の順に多い．宮崎県や関東，近畿，中国，九州・沖縄の各地方で共同研究が増加している傾向がみられる．④企業との共同研究における研究費受入額は，金額が多い順に，関東地方，近畿地方，東海地方，宮崎県，九州・沖縄地方である．東海地方，九州・沖縄地方，および，宮崎県の企業との共同研究において，一件当たりの研究費受入額が増加している傾向がみられ，徐々に大型化が進んでいることが推察される．⑤企業以外の機関を相手先とする共同研究の件数は，宮崎大学が位置する宮崎県内の機関，および，関東地方に位置する機関との共同研究が多い．
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NETLIST FEATURE EXTRACTION FOR CMOS ANALOG CIRCUIT DESIGN WARNING SYSTEM 査読あり
ARIF ABDUL MANNAN, KOICHI TANNO
The International Conference on Machine Learning and Cybernetics (ICMLC) and The International Conference on Wavelet Analysis and Pattern Recognition (ICWAPR) ICMLC-6067 2024年9月
担当区分：責任著者 記述言語：英語 掲載種別：研究論文（国際会議プロシーディングス）
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ARIMURA Kazumasa, MIYAUCHI Ryoichi, TANNO Koichi
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences advpub ( 0 ) 2024年
担当区分：責任著者 記述言語：英語 掲載種別：研究論文（学術雑誌） 出版者・発行元：一般社団法人 電子情報通信学会
In this study, we propose the systematic offset voltage reduction method considering the channel length modulation effect for the two-stage CMOS operational amplifiers (Op-Amps) and comparators. The proposed method employs the half-circuit of the input stage in two-stage Op-Amps as the output stage. Using the proposed method, each terminal voltage of the MOS transistors in the input and output stages is aligned, and the channel length modulation effect can be ignored. To generalize the proposed method, we applied the proposed method to Op-Amps with the cascode active load and differential difference amplifier. The systematic offset voltage was evaluated and compared by simulation using HSPICE with TSMC 0.18 <i>μ</i>m model parameters. Consequently, we confirmed that the proposed method can reduce the systematic offset voltage by 95% or more.
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研究グループ 紹介：宮崎大学 工学部工学科 集積技術研究室 招待あり
淡野 公一
電気学会論文誌． Ａ 142 ( 8 ) NL8_4 - NL8_4 2022年8月
担当区分：筆頭著者, 責任著者 記述言語：日本語 掲載種別：研究論文（学術雑誌） 出版者・発行元：一般社団法人 電気学会
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The Fractional-N All Digital Frequency Locked Loop with Robustness for PVT Variation and Its Application for the Microcontroller Unit 査読あり
Ryoichi MIYAUCHI, Akio YOSHIDA, Shuya NAKANO, Hiroki TAMURA, Koichi TANNO, Yutaka FUKUCHI, Yukio KAWAMURA, Yuki KODAMA, Yuichi SEKIYA
IEICE Transactions on Information and Systems Vol.E104-D ( No. 8 ) 1146 - 1153 2021年8月
担当区分：責任著者 記述言語：英語 掲載種別：研究論文（学術雑誌）
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Deep time-delay Markov network for prediction and modeling the stress and emotions state transition
Prasetio B.H., Tamura H., Tanno K.
Scientific Reports 10 ( 1 ) 2020年12月
記述言語：日本語 掲載種別：研究論文（学術雑誌） 出版者・発行元：Scientific Reports
To recognize stress and emotion, most of the existing methods only observe and analyze speech patterns from present-time features. However, an emotion (especially for stress) can change because it was triggered by an event while speaking. To address this issue, we propose a novel method for predicting stress and emotions by analyzing prior emotional states. We named this method the deep time-delay Markov network (DTMN). Structurally, the proposed DTMN contains a hidden Markov model (HMM) and a time-delay neural network (TDNN). We evaluated the effectiveness of the proposed DTMN by comparing it with several state transition methods in predicting an emotional state from time-series (sequences) speech data of the SUSAS dataset. The experimental results show that the proposed DTMN can accurately predict present emotional states by outperforming the baseline systems in terms of the prediction error rate (PER). We then modeled the emotional state transition using a finite Markov chain based on the prediction result. We also conducted an ablation experiment to observe the effect of different HMM values and TDNN parameters on the prediction result and the computational training time of the proposed DTMN.
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ECG Signal Processing Using Fuzzy Classification for Sudden Cardiac Death Prediction 査読あり
Zainul Abidin, Lalu Arya Taruna Jaya, Ponco Siwindarto, and Koichi Tanno
IEEE 50th International Symposium on Multiple-Valued Logic (ISMVL 2020) 111 - 116 2020年11月
記述言語：英語 掲載種別：研究論文（国際会議プロシーディングス）
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Deep time‐delay Markov network for prediction and modeling the stress and emotions state transition 査読あり
Barlian Henryranu Prasetio, Hiroki Tamura & Koichi Tanno
Scientific Reports 2020年10月
記述言語：英語 掲載種別：研究論文（学術雑誌）
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Emotional Variability Analysis Based I-Vector for Speaker Verification in Under-Stress Conditions 査読あり
Barlian Henryranu Prasetio, Hiroki Tamura and Koichi Tanno
Electronics 9 ( 1420 ) 2020年9月
記述言語：英語 掲載種別：研究論文（学術雑誌）
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Emotional variability analysis based I-vector for speaker verification in under-stress conditions
Prasetio B.H., Tamura H., Tanno K.
Electronics (Switzerland) 9 ( 9 ) 1 - 15 2020年9月
記述言語：日本語 掲載種別：研究論文（学術雑誌） 出版者・発行元：Electronics (Switzerland)
Emotional conditions cause changes in the speech production system. It produces the differences in the acoustical characteristics compared to neutral conditions. The presence of emotion makes the performance of a speaker verification system degrade. In this paper, we propose a speaker modeling that accommodates the presence of emotions on the speech segments by extracting a speaker representation compactly. The speaker model is estimated by following a similar procedure to the i-vector technique, but it considerate the emotional effect as the channel variability component. We named this method as the emotional variability analysis (EVA). EVA represents the emotion subspace separately to the speaker subspace, like the joint factor analysis (JFA) model. The effectiveness of the proposed system is evaluated by comparing it with the standard i-vector system in the speaker verification task of the Speech Under Simulated and Actual Stress (SUSAS) dataset with three different scoring methods. The evaluation focus in terms of the equal error rate (EER). In addition, we also conducted an ablation study for a more comprehensive analysis of the EVA-based i-vector. Based on experiment results, the proposed system outperformed the standard i-vector system and achieved state-of-the-art results in the verification task for the under-stressed speakers.
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Prasetio B.H., Tamura H., Tanno K.
2020 Joint 9th International Conference on Informatics, Electronics and Vision and 2020 4th International Conference on Imaging, Vision and Pattern Recognition, ICIEV and icIVPR 2020 2020年8月
記述言語：日本語 掲載種別：研究論文（学術雑誌） 出版者・発行元：2020 Joint 9th International Conference on Informatics, Electronics and Vision and 2020 4th International Conference on Imaging, Vision and Pattern Recognition, ICIEV and icIVPR 2020
Speech activity detection (SAD) or sometimes called voice activity detection (VAD), is a crucial part of most speech-related applications. The SAD system serves to ensure the primary system processes only speech segments. Many speech-based systems have reported that detection accuracy is thanks to the robustness of their SAD system. Various SAD methods have been explored and enhanced in addressing noisy environments, but a few of them notice the emotional condition of the speakers. Whereas, in real conditions, emotions (such as stress) can pose a considerable impact on SAD system performance. In this paper, we propose a compact SAD system that is able to harmonize with the altered speech characteristics due to the presence of emotion and also powerful in high noise conditions. Since there is a similarity between emotional effect and channel effect, the advantages of the proposed SAD system is the applied of a new channel compensation scheme (termed as embedded discriminant analysis, EDA) that works in the i-vector space. We design the EDA in such a way so that it could compensate the presence of emotional condition. EDA transforms original i-vector to a lower-dimensional denoise embedding space. We develop EDA as simple and efficient as the linear discriminant analysis (LDA). The cosine similarity algorithm is applied to calculate the resemblance score between the audio target and the speech/non-speech models, and also for deciding the decision threshold. The effectiveness of the proposed SAD system is evaluated in the clustering task of Speech Under Simulated and Actual Stress (SUSAS) data, that aimed for the stress speech clustering (SSC) system. Contribution-We propose a SAD system which not only strong in noisy environments but also be able to compensate the presence of emotional conditions.
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Prasetio B.H., Tamura H., Tanno K.
Artificial Life and Robotics 25 ( 2 ) 233 - 240 2020年5月
記述言語：日本語 掲載種別：研究論文（学術雑誌） 出版者・発行元：Artificial Life and Robotics
Stress causes a speaker’s voice characteristics to be changed. Emotional stress alters a person’s speech pattern such that it is distributed non-normally along the temporal dimension. Thus, the methods for identifying the gender of a non-stressed speaker were no longer effective in recognizing the gender of a speaker in stressful conditions. To address this issue, a new gender identification framework is proposed. We leveraged i-vector for capturing gender information on each speech segment. Then the long short-term memory dynamically handled all speech temporal context features and learned the long-term dependency from the input. We evaluated the effectiveness, in terms of accuracy and the number of iterations to saturate, of the proposed method by comparing it with the baseline methods in their respective abilities to identify the speaker’s gender from conversations with different durations. By learning the gender information encoded in long-term dependencies, our proposed method outperforms the baseline methods and is able to correctly identify the speaker’s gender in all conversation types.
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High-PSRR, Low-Voltage CMOS Current Mode Reference Circuit Using Self-Regulator with Adaptive Biasing Technique 査読あり
Kenya Kondo, Hiroki Tamura, Koichi Tanno
IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences E103-A ( 2 ) 486 - 491 2020年2月
記述言語：英語 掲載種別：研究論文（学術雑誌）
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The long short-term memory based on i-vector extraction for conversational speech gender identification approach 査読あり
Barlian Henryranu Prasetio, Hiroki Tamura, Koichi Tanno
Artificial Life and Robotics 2020年1月
記述言語：英語 掲載種別：研究論文（学術雑誌）
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Semi-supervised deep time-delay embedded clustering for stress speech analysis 査読あり
Prasetio B., Tamura H., Tanno K.
Electronics (Switzerland) 8 ( 11 ) 2019年11月