論文 - 淡野　公一

Wide-input range variable resistor circuit using an FG-MOSFET

共著者：M. Kushima, K. Tanno, O. Ishizuka

IEICE Trans. on Fundamentals, Vol.E86-A, No.12, 3294-3296   2003年12月

Low-voltage and wide-bandwidth CMOS operational transconductance amplifier using combiners and its application to an equalizer

共著者：K. Tanno, K. Kondo, S. Harada, O. Ishizuka

Proc. of The 2003 International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC), Vol. 1, 53-56   2003年7月

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記述言語：英語   掲載種別：研究論文（学術雑誌）  

Wide input-range four-quadrant analog multiplier using floating-gate MOSFET's

共著者：D. Zhu, K. Tanno, O. Ishizuka

IEICE Trans. on Fundamentals, Vol.E86-A, No.7, 1759-1765   2003年7月

Improvement of linear variable resistor circuit using multiple-input FG-MOSFETs

共著者：M. Kushima, K. Tanno, O. Ishizuka

Proc. of The 2003 International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC), Vol. 1, 329-332   2003年7月

A 3.0-V highly linear CMOS OTA and its application to active filters

共著者：D. Zhu, K. Tanno, O. Ishizuka

Proc. of The 2003 International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC), Vol. 1, 69-72   2003年7月

Low-power and wide-input-range voltage controlled linear variable resistor using an FG-MOSFET and its application

共著者：M. Kushima, K. Tanno, O. Ishizuka

IEICE Trans. on Fundamentals, Vol.E86-A, No.2, 342-349   2003年2月

A novel binary-to-residue conversion algorithm for moduli (2n-1, 2n, 2n+2a)

共著者：M. Syuto, E. Satake, K. Tanno, O. Ishizuka

Proc. of The 2002 International Conference on Circuits/Systems Computers and Communications (ITC-CSCC 2002), Vol.1, 662-665   2002年7月

Multi-valued flip-flop with neuron-CMOS NMIN circuits

共著者：M. Inaba, K. Tanno, O. Ishizuka

Proc. of 32st IEEE International Symposium on Multiple-Valued Logic, Vol.32, 282-288   2002年5月

A high-speed binary to residue converter using a signed-digit number representation

共著者：M. Syuto, E. Satake, K. Tanno, O. Ishizuka

IEICE Trans. on Information and Systems, Vol.E85-D, No.5, 903-905   2002年5月

Synthesis and implementation of multi-input variable-threshold functions

共著者：M. Syuto, K. Tanno, O. Ishizuka

MULTIPLE-VALUED LOGIC - An International Journal, Vol.8, No.1, 71-87   2002年2月

Voltage-mode variable threshold circuits with neuron MOS transistors for multi-valued logic

共著者：M. Inaba, J. Shen, K. Tanno, O. Ishizuka

MULTIPLE-VALUED LOGIC - An International Journal, Vol.8, No.1, 89-126   2002年2月

MAX and MIN Circuits with Neuron-MOS Analog Inverters

共著者：H. Tanaka, M. Inaba, K. Tanno, O. Ishizuka

Proc. of 2001 International Symposium on Nonlinear Theory and its Applications (NOLTA2001), Vol.2, 597-600   2001年10月

Current-Mode Differential Circuit for High-Performance Multi-Valued Logic Circuits

共著者：K. Maruyama, M. Nagasato, K. Tanno, O. Ishizuka

Proc. of The Second Korea-Japan Joint Symposium on Multiple-Valued Logic, Vol.1, 62-65   2001年8月

Voltage-Mode Multi-Input MIN and MAX Circuits for Multi-Valued Logic Circuits

共著者：K. Kondo, H. Magata, M. Inaba, K. Tanno, O. Ishizuka

Proc. of The Second Korea-Japan Joint Symposium on Multiple-Valued Logic, Vol.1, 152-155   2001年8月

Simple digitally programmable attenuator using FG-MOSFETs

共著者：K. Tanno, H. Tanaka, M. Syuto, O. Ishizuka

Electronics Letters, Vol.37, No.10, 610-611   2001年5月

Realization of NMAX and NMIN Functions with Voltage Comparators

共著者：M. Inaba, K. Tanno, O. Ishizuka

Proc. of 31st IEEE International Symposium on Multiple-Valued Logic, Vol.31, 27-32   2001年5月

Voltage-Controlled Linear Variable Resistor Using a Floating-Gate MOSFET

共著者：M. Kushima, K. Tanno, H. Kumagai, O. Ishizuka

Proc. of 2001 IEEJ International Analog VLSI Workshop, Vol.1, 57-61   2001年5月

Characteristics of neuron MOS LSI for multi-valued logic

共著者：M. Inaba, J. Shen, K. Tanno, O. Ishizuka

Proc. of Int. Symp. on Nonlinear Theory and its Application, Vol.1, No.6-B, 405-408   2000年9月

Multi-valued logic pass gate network using neuron-MOS transistors

共著者：J. Shen, K. Tanno, O. Ishizuka

Proc. of IEEE Int. Symp. on Multiple-Valued Logic, Vol.30, 15-20   2000年5月

Four-quadrant CMOS current-mode multiplier independent of device parameters

共著者：K. Tanno, O. Ishizuka, Z. Tang

IEEE Trans. on Circuits and Systems II, Vol.47, No.5, 473-477   2000年5月