Papers - KATAYAMA Tetsuro
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形式仕様を用いたデシジョンテーブル生成手法の提案 Reviewed
西川拳太, 片山徹郎, 喜多義弘, 山場久昭, 岡崎直宣
情報処理学会 ソフトウェアエンジニアリングシンポジウム2014(SES2014) 39 - 44 2014.9
Language：Japanese Publishing type：Research paper (scientific journal)
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Shoichiro Kitano, Tetsuro Katayama
IPSJ SIG Notes 2014 ( 23 ) 1 - 8 2014.7
Language：Japanese Publishing type：Research paper (scientific journal) Publisher：Information Processing Society of Japan (IPSJ)
In multi-threaded programs, it is difficult to reproduce the situation when existing bugs are discovered because execution of the multi-threaded programs is usually non-deterministic. Therefore, it is difficult to obtain the information for understanding the behavior of the program when bugs are discovered. And, to identify the cause of bags becomes difficult. This paper proposes a supporting method for debugging to reproduce Java multi-threaded programs by visualizing the behavior of the programs with Petri-net. Conventional Petri-net cannot enough express the complicated behavior of the multi-threaded programs. Therefore, we extend Petri-net. We have confirmed the effectiveness of our method by implementing a prototype of a debugging supporting tool based on our method. In experiment for confirmation, to use our tool could identify the cause of the bug in about 33.6% of the time it takes without our tool. This result shows that our method and tool can improve efficiency in debugging for the multi-threaded programs.
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形式手法を用いたテスト設計時におけるデシジョンテーブル生成支援手法の提案
西川拳太, 片山徹郎
宮崎大学工学部紀要 ( 43 ) 257 - 262 2014.7
Language：Japanese Publishing type：Research paper (bulletin of university, research institution)
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データ遷移の可視化手法によるバグの原因特定支援について
中村紘人, 片山徹郎
宮崎大学工学部紀要 ( 43 ) 249 - 256 2014.7
Language：Japanese Publishing type：Research paper (bulletin of university, research institution)
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ペトリネットを用いたJavaマルチスレッドプログラムの実行を再現することによるデバッグ支援手法の提案
北野翔一郎, 片山徹郎
宮崎大学工学部紀要 ( 43 ) 243 - 248 2014.7
Language：Japanese Publishing type：Research paper (bulletin of university, research institution)
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Proposal of a Supporting Method to Generate a Decision Table from the Formal Specification Reviewed
K. Nishikawa, T. Katayama, Y. Kita, H. Yamaba, and N. Okazaki
Proc. Int'l Conf. on Artificial Life and Robotics (ICAROB 2014) 222 - 225 2014.1
Language：English Publishing type：Research paper (scientific journal)
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Proposal of a Supporting Method for Debugging to Reproduce Java Multi-threaded Programs by Petri-Net Reviewed
S. Kitano, T. Katayama, Y. Kita, H. Yamaba, and N. Okazaki
Proc. Int'l Conf. on Artificial Life and Robotics (ICAROB 2014) 218 - 221 2014.1
Language：English Publishing type：Research paper (scientific journal)
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Proposal of a Method to Build Markov Chain Usage Model from UML Diagrams for Communication Delay Testing in Distributed Systems Reviewed
Z. Zhao, T. Katayama, Y. Kita, H. Yamaba, and N. Okazaki
Proc. Int'l Conf. on Artificial Life and Robotics (ICAROB 2014) 214 - 217 2014.1
Language：English Publishing type：Research paper (scientific journal)
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Proposal of a Visualizing Method of Data Transitions to Support Debugging for Java Programs Reviewed
H. Nakamura, T. Katayama, Y. Kita, H. Yamaba, and N. Okazaki
Proc. Int'l Conf. on Artificial Life and Robotics (ICAROB 2014) 210 - 213 2014.1
Language：English Publishing type：Research paper (scientific journal)
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Combinatorial test architecture design using viewpoint diagram
Nishi Y., Katayama T., Yoshizawa S.
Proceedings - IEEE 6th International Conference on Software Testing, Verification and Validation Workshops, ICSTW 2013 295 - 300 2013.9
Language：Japanese Publishing type：Research paper (scientific journal) Publisher：Proceedings - IEEE 6th International Conference on Software Testing, Verification and Validation Workshops, ICSTW 2013
Software test has recently been a large-scale and complicated artifact, as is the software itself. It is necessary to reduce huge combinatorial test cases. This paper focuses on reduction of test parameters and combinations in test architectural design. First we will mention the test architecture design phase in TDLC: Test Development Life Cycle. Second we will introduce NGT: Notation for Generic Testing, which is a set of concepts or notation for design of software test architecture. This paper shows four examples of test architecture design patterns: Interaction-Viewpoint Conversion pattern, Interaction Cluster Partitioning Pattern, Interaction Demotion Pattern and Interaction Necessity Analysis. © 2013 IEEE.
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Proposal of testing diagrams for visualizing test cases
Urata S., Katayama T.
Proceedings - IEEE 6th International Conference on Software Testing, Verification and Validation, ICST 2013 483 - 484 2013.9
Language：Japanese Publishing type：Research paper (scientific journal) Publisher：Proceedings - IEEE 6th International Conference on Software Testing, Verification and Validation, ICST 2013
A software system becomes a large scale in recent years. As a result, test cases used in software testing have become a large scale. It is difficult to understand where the software system is tested by a large quantity of test cases. For this reason, testing diagrams to visualize test cases are proposed. To generate the testing diagrams, the test case and UML (Unified Modeling Language) diagram are compared and their common information is added to the UML diagram. This paper uses communication diagram and state machine diagram. Generating the testing diagrams can overlook the whole test cases. As a result, we can easily understand where the software system is tested by test cases. Moreover, the testing diagrams support that you find faults in the test cases and/or UML diagrams. © 2013 IEEE.
DOI： 10.1109/ICST.2013.81
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テストケースの可視化を実現するテスト用ダイアグラムの提案 Reviewed
浦田聖也, 片山徹郎
情報処理学会 ソフトウェアエンジニアリングシンポジウム2013(SES2013) 2013.9
Language：Japanese Publishing type：Research paper (scientific journal)
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A conversion method from an ETSC to a timed Petri net to improve the matrix-based discrete event controller and its unified support system Reviewed
H. Yamaba, S. Kitano, K. Takatsuka, T. Katayama, N. Okazaki, and S. Tomita
Proc. 17th Int'l Conf. on Knowledge-Based and Intelligent Information and Engineering Systems (KES2013) 660 - 669 2013.9
Language：English Publishing type：Research paper (international conference proceedings)
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テストケースの可視化を目的としたテスト用ダイアグラムの提案
浦田聖也, 片山徹郎
宮崎大学工学部紀要 ( 42 ) 263 - 269 2013.8
Language：Japanese Publishing type：Research paper (bulletin of university, research institution)
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''Matrix-Bases Discrete-Event System Controller''を閣僚するためのETSCから時間ペトリネットへの変換手法とその統一的支援システム
北野翔一郎, 山場久昭, 高塚佳代子, 片山徹郎, 岡崎直直, 冨田重幸
火の国情報シンポジウム2013 CD-ROM 2013.3
Language：Japanese Publishing type：Research paper (scientific journal)
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Combinatorial Test Architecture Design Using Viewpoint Diagram Reviewed
Y. Nishi, T. Katayama, and S. Yoshizawa
2nd Int'l Works. on Combinatorial Testing (IWCT 2013) 2013.3
Language：English Publishing type：Research paper (scientific journal)
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Proposal of Testing Diagrams for Visualizing Test Cases Reviewed
S. Urata and T. Katayama
6th Int'l Conf. on Software Testing, Verification and Validation (ICST2013) 2013.3
Language：English Publishing type：Research paper (scientific journal)
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MATSUOKA Shingo, KATAYAMA Tetsuro
Technical report of IEICE. SS 112 ( 373 ) 37 - 42 2013.1
Language：Japanese Publishing type：Research paper (scientific journal) Publisher：The Institute of Electronics, Information and Communication Engineers
This paper aims to reduce the effort spent on understanding and confirming the testing progress by visualizing the progress of unit testing in software development in real-time. As an approach to achieve the goal, an automatic unit testing and visualization tool " Jvis " (Tool for Java programs to visualize unit testing) has been implemented Jvis is executed the automated testing based on CO (statement coverage) and C1 (branch coverage) for the test target program. Jvis visualizes current testing progress in real-time. As a result of the experiment applying programs with the defect to Jvis, each examinees could detect the defect in short time Hence, the effort spent on understanding and confirming the testing progress can be reduced by real-time visualization of the testing porogress from this experiment.
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DDoS攻撃者によるIPトレースバックに対する妨害手法とその対策に関する検討 Reviewed
川端良樹, 喜多義弘, 山場久昭, 油田健太郎, 朴美娘, 片山徹郎, 岡崎直宣
日本セキュリティ・マネジメント学会誌 26 ( 3 ) 15 - 32 2013.1
Language：Japanese Publishing type：Research paper (scientific journal)
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Yamaba H., Kitano S., Takatsuka K., Katayama T., Okazaki N., Tomita S.
Procedia Computer Science 22 467 - 476 2013
Language：Japanese Publishing type：Research paper (scientific journal) Publisher：Procedia Computer Science
The matrix-based discrete-event system controller (MDEC) framework, which is a sophisticated framework proposed by Jose Mireles et al., is a promising method for designing control systems for discrete manufacturing systems. In a previous study, we improved the MDEC framework by introducing a timed Petri net and an expanded timed-state-chart (ETSC) that was developed in our laboratory in order to describe complex behavior of discrete manufacturing systems. In the present study, a computer system supporting the design of such control systems was implemented based on the improved framework (MDEC2). ETSC models, which users draw through a GUI, are converted into timed Petri nets in the form of matrices, and such matrices are embedded into controllers of MDEC2. Through a series of experiments, we confirmed that the obtained controllers functioned well. © 2013 The Authors.