Papers - KATAYAMA Tetsuro
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DDoS攻撃者によるIPトレースバックに対する妨害手法とその対策に関する検討 Reviewed
川端良樹, 喜多義弘, 山場久昭, 油田健太郎, 朴美娘, 片山徹郎, 岡崎直宣
日本セキュリティ・マネジメント学会誌 26 ( 3 ) 15 - 32 2013.1
Language：Japanese Publishing type：Research paper (scientific journal)
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Yamaba H., Kitano S., Takatsuka K., Katayama T., Okazaki N., Tomita S.
Procedia Computer Science 22 467 - 476 2013
Language：Japanese Publishing type：Research paper (scientific journal) Publisher：Procedia Computer Science
The matrix-based discrete-event system controller (MDEC) framework, which is a sophisticated framework proposed by Jose Mireles et al., is a promising method for designing control systems for discrete manufacturing systems. In a previous study, we improved the MDEC framework by introducing a timed Petri net and an expanded timed-state-chart (ETSC) that was developed in our laboratory in order to describe complex behavior of discrete manufacturing systems. In the present study, a computer system supporting the design of such control systems was implemented based on the improved framework (MDEC2). ETSC models, which users draw through a GUI, are converted into timed Petri nets in the form of matrices, and such matrices are embedded into controllers of MDEC2. Through a series of experiments, we confirmed that the obtained controllers functioned well. © 2013 The Authors.
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Javaプログラムのための単体テスト並列実行ツールの試作 Reviewed
西川拳太, 松岡慎吾, 片山徹郎
ソフトウェアテストシンポジウム2012九州(JaSST'12 Kyushu) 30 - 33 2012.11
Language：Japanese Publishing type：Research paper (scientific journal)
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テストケースの可視化を目的としたテスト用状態マシン図作成手法の提案 Reviewed
浦田聖也, 片山徹郎
ソフトウェアテストシンポジウム2012九州(JaSST'12 Kyushu) 30 - 33 2012.11
Language：Japanese Publishing type：Research paper (scientific journal)
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Javaプログラムを対象とした単体テスト可視化ツール``Jvis''の開発 Reviewed
松岡慎吾, 喜多義弘, 片山徹郎
情報処理学会 ソフトウェアエンジニアリングシンポジウム2012(SES2012) 2012.8
Language：Japanese Publishing type：Research paper (scientific journal)
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シミュレータ作成の手間を削減可能な 二部構成シミュレータ設計手法の提案
川元卓, 喜多義弘, 片山徹郎
宮崎大学工学部紀要 ( 41 ) 269 - 276 2012.8
Language：Japanese Publishing type：Research paper (bulletin of university, research institution)
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Javaプログラムを対象とした単体テスト自動実行および 可視化ツール``Jvis''の開発
松岡慎吾, 喜多義弘, 片山徹郎
宮崎大学工学部紀要 ( 41 ) 261 - 268 2012.8
Language：Japanese Publishing type：Research paper (bulletin of university, research institution)
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KITA Yoshihiro, KATAYAMA Tetsuro, TOMITA Shigeyuki
The IEICE transactions on information and systems (Japanese edetion) 95 ( 4 ) 855 - 869 2012.4
Language：Japanese Publishing type：Research paper (scientific journal) Publisher：The Institute of Electronics, Information and Communication Engineers
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Javaプログラム読解支援のためのプログラム可視化ツールAvisの実装と評価 Reviewed
喜多義弘, 片山徹郎, 冨田重幸
電子情報通信学会論文誌 J95-D ( 4 ) 855 - 869 2012.4
Language：Japanese Publishing type：Research paper (scientific journal)
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Prototype of an Automatic Unit Testing Tool with Random Testing for Java Programs Reviewed
S. Matsuoka, Y. Kita, and T. Katayama
Proc. 22nd Int'l Sympo. on Softw. Reliability Eng. (ISSRE2011) 2011.12
Language：English Publishing type：Research paper (international conference proceedings)
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Formal Verification of Software Designs in Hierarchical State Transition Matrix with SMT-based Bounded Model Checking Reviewed
W. Kong, N. Katahira, M. Watanabe, T. Katayama, K. Hisazumi, and A. Fukuda
Proc. 2011 Asia-Pacific Softw. Eng. Conf. (APSEC 2011) 81 - 88 2011.12
Language：English Publishing type：Research paper (international conference proceedings)
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Motivation to Establish a Concept of Test Architecture Invited
T. Katayama
Proc. International Workshop on Software Test Architecture (InSTA) 2011.12
Language：English Publishing type：Research paper (international conference proceedings)
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Kong W., Katahira N., Watanabe M., Katayama T., Hisazumi K., Fukuda A.
Proceedings - Asia-Pacific Software Engineering Conference, APSEC 81 - 88 2011.12
Language：Japanese Publishing type：Research paper (scientific journal) Publisher：Proceedings - Asia-Pacific Software Engineering Conference, APSEC
Hierarchical State Transition Matrix (HSTM) is a table-based modeling language for developing designs of software systems. Although widely used and adopted by (particularly Japanese) software industry, there is still lack of mechanized formal verification supports for conducting rigorous and automatic analysis to improve reliability of HSTM designs. In this paper, we first present a formalization of HSTM designs as state transition systems. Consequentially, based on this formalization, we propose a symbolic encoding approach, through which correctness of a HSTM design with respect to LTL properties could be represented as Bounded Model Checking (BMC) problems that could be determined by Satisfiability Modulo Theories (SMT) solving. We have implemented our encoding approach in a tool called Garakabu2 with the state-of-the-art SMT solver CVC3 as its back-ended solver. Furthermore, in our preliminary experiments, a conceptually simple but steadily effective way of accelerating SMT solving for HSTM designs is investigated and reported. © 2011 IEEE.
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Proposal of an Execution Paths Indication Method for Integration Testing by Using an Automatic Visualization Tool `Avis' Reviewed
Y. Kita, T. Katayama, and S. Tomita
Proc. 5th World Congress for Softw. Quality(5WCSQ) 2011.11
Language：English Publishing type：Research paper (international conference proceedings)
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コーディングとテストの並列開発手法実現のための一考察 Reviewed
大久保暢人, 松岡慎吾, 喜多義弘, 片山徹郎
ソフトウェアテストシンポジウム2011九州(JaSST'11 Kyushu) 30 - 32 2011.11
Language：Japanese Publishing type：Research paper (scientific journal)
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An SMT-based approach to bounded model checking of designs in communicating state transition matrix
Kong W., Katahira N., Qian W., Watanabe M., Katayama T., Fukuda A.
Proceedings - 2011 International Conference on Computational Science and Its Applications, ICCSA 2011 159 - 167 2011.9
Language：Japanese Publishing type：Research paper (scientific journal) Publisher：Proceedings - 2011 International Conference on Computational Science and Its Applications, ICCSA 2011
State Transition Matrix (STM) is a table-based modeling language for developing designs of software systems. Although widely accepted and used in software industry, there is lack of formal verification supports for conducting rigorous analysis to improve reliability of STM designs. In this paper, we present a symbolic encoding approach for STM designs that employ message passing as the means of communication, through which correctness of a STM design with respect to invariant properties could be Bounded Model Checked (BMC) by using Satisfiability Modulo Theories (SMT) solving techniques. We have built a prototype implementation of the proposed encoding and the state-of-the-art SMT solver - Yices, is used in our experiments as a back-end tool to evaluate the effectiveness of our approach. In addition, two approaches for accelerating SMT solving by introducing additional knowledge are proposed and their effectiveness is shown by our preliminary experimental results. © 2011 IEEE.
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ソフトウェア要求仕様書に基づいたテスト項目作成手法の提案 Reviewed
喜多義弘, 鈴木三紀夫, 秋山浩一, 片山徹郎, 西康晴
情報処理学会 ソフトウェアエンジニアリングシンポジウム2011(SES2011) 2011 ( 2 ) 1 - 6 2011.9
Language：Japanese Publishing type：Research paper (scientific journal)
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組込みソフトウェア開発支援のための命令セットシミュレータ(ISS)作成支援ツールの試作
東園修平, 片山徹郎
宮崎大学工学部紀要 ( 40 ) 263 - 268 2011.8
Language：Japanese Publishing type：Research paper (bulletin of university, research institution)
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ランダムテスト手法を用いたJava プログラム単体テスト自動実行ツールの試作 Reviewed
松岡慎吾, 喜多義弘, 片山徹郎
ソフトウェア・シンポジウム SS2011 2011.6
Language：Japanese Publishing type：Research paper (scientific journal)
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An SMT-based Approach to Bounded Model Checking of Designs in Communicating State Transition Matrix Reviewed
W. Kong, N. Katahira, W. Qian, M. Watanabe, T. Katayama, and A. Fukuda
11th Int'l Conf. on Computational Sci. and Its Application (ICCSA 2011) 159 - 167 2011.6
Language：English Publishing type：Research paper (international conference proceedings)